// Copyright 2004-present Facebook. All Rights Reserved.

#pragma once

#include <sai.h>

typedef enum _sai_port_serdes_extensions_attr_t {
  SAI_PORT_SERDES_ATTR_EXT_FAKE_RX_CTLE_CODE =
      SAI_PORT_SERDES_ATTR_CUSTOM_RANGE_START,
  SAI_PORT_SERDES_ATTR_EXT_FAKE_RX_DSP_MODE,
  SAI_PORT_SERDES_ATTR_EXT_FAKE_RX_AFE_TRIM,
  SAI_PORT_SERDES_ATTR_EXT_FAKE_RX_AC_COUPLING_BYPASS,
  SAI_PORT_SERDES_ATTR_EXT_FAKE_RX_AFE_ADAPTIVE_ENABLE,
  SAI_PORT_SERDES_ATTR_EXT_RX_CHANNEL_REACH,
  SAI_PORT_SERDES_ATTR_EXT_RX_DIFF_ENCODER_EN,
  SAI_PORT_SERDES_ATTR_EXT_RX_FBF_COEF_INIT_VAL,
  SAI_PORT_SERDES_ATTR_EXT_RX_FBF_LMS_ENABLE,
  SAI_PORT_SERDES_ATTR_EXT_RX_INSTG_SCAN_OPTIMIZE,
  SAI_PORT_SERDES_ATTR_EXT_RX_INSTG_TABLE_END_ROW,
  SAI_PORT_SERDES_ATTR_EXT_RX_INSTG_TABLE_START_ROW,
  SAI_PORT_SERDES_ATTR_EXT_RX_PARITY_ENCODER_EN,
  SAI_PORT_SERDES_ATTR_EXT_RX_THP_EN,
  SAI_PORT_SERDES_ATTR_EXT_RX_INSTG_BOOST1_STRT,
  SAI_PORT_SERDES_ATTR_EXT_RX_INSTG_BOOST1_STEP,
  SAI_PORT_SERDES_ATTR_EXT_RX_INSTG_BOOST1_STOP,
  SAI_PORT_SERDES_ATTR_EXT_RX_INSTG_BOOST2_OR_HR_STRT,
  SAI_PORT_SERDES_ATTR_EXT_RX_INSTG_BOOST2_OR_HR_STEP,
  SAI_PORT_SERDES_ATTR_EXT_RX_INSTG_BOOST2_OR_HR_STOP,
  SAI_PORT_SERDES_ATTR_EXT_RX_INSTG_C1_START_1P7,
  SAI_PORT_SERDES_ATTR_EXT_RX_INSTG_C1_STEP_1P7,
  SAI_PORT_SERDES_ATTR_EXT_RX_INSTG_C1_STOP_1P7,
  SAI_PORT_SERDES_ATTR_EXT_RX_INSTG_DFE_START_1P7,
  SAI_PORT_SERDES_ATTR_EXT_RX_INSTG_DFE_STEP_1P7,
  SAI_PORT_SERDES_ATTR_EXT_RX_INSTG_DFE_STOP_1P7,
  SAI_PORT_SERDES_ATTR_EXT_RX_INSTG_ENABLE_SCAN,
  SAI_PORT_SERDES_ATTR_EXT_RX_INSTG_SCAN_USE_SR_SETTINGS,
  SAI_PORT_SERDES_ATTR_EXT_RX_CDR_CFG_OV_EN,
  SAI_PORT_SERDES_ATTR_EXT_RX_CDR_TDET_1ST_ORD_STEP_OV_VAL,
  SAI_PORT_SERDES_ATTR_EXT_RX_CDR_TDET_2ND_ORD_STEP_OV_VAL,
  SAI_PORT_SERDES_ATTR_EXT_RX_CDR_TDET_FINE_STEP_OV_VAL,
  SAI_PORT_SERDES_ATTR_EXT_RX_DCW_EN,
  SAI_PORT_SERDES_ATTR_EXT_RX_DCW_STEP_COARSE_OV_VAL,
  SAI_PORT_SERDES_ATTR_EXT_RX_DCW_STEP_FINE_OV_VAL,
  SAI_PORT_SERDES_ATTR_EXT_RX_DCW_OV_EN,
  SAI_PORT_SERDES_ATTR_EXT_TX_PARITY_ENCODER_EN,
  SAI_PORT_SERDES_ATTR_EXT_TX_THP_EN,
  SAI_PORT_SERDES_ATTR_EXT_TX_LUT_MODE,
  SAI_PORT_SERDES_ATTR_EXT_TX_DIFF_ENCODER_EN,
  SAI_PORT_SERDES_ATTR_EXT_TX_DIG_GAIN,
  SAI_PORT_SERDES_ATTR_EXT_TX_FFE_COEFF_0,
  SAI_PORT_SERDES_ATTR_EXT_TX_FFE_COEFF_1,
  SAI_PORT_SERDES_ATTR_EXT_TX_FFE_COEFF_2,
  SAI_PORT_SERDES_ATTR_EXT_TX_FFE_COEFF_3,
  SAI_PORT_SERDES_ATTR_EXT_TX_FFE_COEFF_4,
  SAI_PORT_SERDES_ATTR_EXT_TX_DRIVER_SWING,
  SAI_PORT_SERDES_ATTR_EXT_TX_LDO_BYPASS,
  SAI_PORT_SERDES_ATTR_EXT_RX_LDO_BYPASS,
  SAI_PORT_SERDES_ATTR_EXT_RX_FFE_LENGTH_BITMAP,
  SAI_PORT_SERDES_ATTR_EXT_RX_FFE_LMS_DYNAMIC_GATING_EN
} sai_port_serdes_extensions_attr_t;

typedef enum _sai_switch_extensions_attr_t {
  SAI_SWITCH_ATTR_EXT_FAKE_LED = SAI_SWITCH_ATTR_END,
  SAI_SWITCH_ATTR_EXT_FAKE_LED_RESET,
  SAI_SWITCH_ATTR_EXT_FAKE_ACL_FIELD_LIST,
  SAI_SWITCH_ATTR_DEFAULT_EGRESS_BUFFER_POOL_SHARED_SIZE,
  SAI_SWITCH_ATTR_EXT_FAKE_HW_ECC_ERROR_INITIATE,
  SAI_SWITCH_ATTR_ISSU_CUSTOM_DLL_PATH,
  SAI_SWITCH_ATTR_EXT_RESTART_ISSU,
  SAI_SWITCH_ATTR_FORCE_TRAFFIC_OVER_FABRIC,
  SAI_SWITCH_ATTR_EXT_WARM_BOOT_TARGET_VERSION,
  SAI_SWITCH_ATTR_FABRIC_REMOTE_REACHABLE_PORT_LIST,
  SAI_SWITCH_ATTR_VOQ_LATENCY_MIN_LOCAL,
  SAI_SWITCH_ATTR_VOQ_LATENCY_MAX_LOCAL,
  SAI_SWITCH_ATTR_VOQ_LATENCY_MIN_LEVEL_1,
  SAI_SWITCH_ATTR_VOQ_LATENCY_MAX_LEVEL_1,
  SAI_SWITCH_ATTR_VOQ_LATENCY_MIN_LEVEL_2,
  SAI_SWITCH_ATTR_VOQ_LATENCY_MAX_LEVEL_2,
  SAI_SWITCH_ATTR_REACHABILITY_GROUP_LIST,
  SAI_SWITCH_ATTR_FABRIC_LLFC_THRESHOLD,
  SAI_SWITCH_ATTR_SRAM_FREE_PERCENT_XOFF_TH,
  SAI_SWITCH_ATTR_SRAM_FREE_PERCENT_XON_TH,
  SAI_SWITCH_ATTR_MAX_SYSTEM_PORT_ID,
  SAI_SWITCH_ATTR_MAX_LOCAL_SYSTEM_PORT_ID,
  SAI_SWITCH_ATTR_MAX_SYSTEM_PORTS,
  SAI_SWITCH_ATTR_MAX_VOQS,
  SAI_SWITCH_ATTR_FABRIC_CLLFC_TX_CREDIT_TH,
  SAI_SWITCH_ATTR_VOQ_DRAM_BOUND_TH,
  SAI_SWITCH_ATTR_COND_ENTROPY_REHASH_PERIOD_US,
  SAI_SWITCH_ATTR_SHEL_SRC_IP,
  SAI_SWITCH_ATTR_SHEL_DST_IP,
  SAI_SWITCH_ATTR_SHEL_SRC_MAC,
  SAI_SWITCH_ATTR_SHEL_PERIODIC_INTERVAL,
  SAI_SWITCH_ATTR_FIRMWARE_CORE_TO_USE,
  SAI_SWITCH_ATTR_FIRMWARE_LOG_PATH_NAME,
  SAI_SWITCH_ATTR_MAX_SWITCH_ID,
  SAI_SWITCH_ATTR_SFLOW_AGGR_NOF_SAMPLES,
  SAI_SWITCH_ATTR_SDK_DUMP_LOG_PATH_NAME,
  SAI_SWITCH_ATTR_FIRMWARE_OBJECTS,
  SAI_SWITCH_ATTR_TC_RATE_LIMIT_LIST,
  SAI_SWITCH_ATTR_PFC_TC_DLD_TIMER_INTERVAL,
  SAI_SWITCH_ATTR_NUMBER_OF_PIPES,
  SAI_SWITCH_ATTR_PIPELINE_OBJECTS,
  SAI_SWITCH_ATTR_DISABLE_SLL_AND_HLL_TIMEOUT,
  SAI_SWITCH_ATTR_ASIC_REVISION,
  SAI_SWITCH_ATTR_CREDIT_REQUEST_PROFILE_SCHEDULER_MODE,
  SAI_SWITCH_ATTR_MODULE_ID_TO_CREDIT_REQUEST_PROFILE_PARAM_LIST,
  SAI_SWITCH_ATTR_TRIGGER_SIMULATED_ECC_CORRECTABLE_ERROR,
  SAI_SWITCH_ATTR_TRIGGER_SIMULATED_ECC_UNCORRECTABLE_ERROR,
  SAI_SWITCH_ATTR_DEFAULT_CPU_EGRESS_BUFFER_POOL,
  SAI_SWITCH_ATTR_TECH_SUPPORT_TYPE,
  SAI_SWITCH_ATTR_MODULE_ID_FABRIC_PORT_LIST,
  SAI_SWITCH_ATTR_LOCAL_SYSTEM_PORT_ID_RANGE_LIST,
  SAI_SWITCH_ATTR_PFC_MONITOR_ENABLE,
  SAI_SWITCH_ATTR_CABLE_PROPAGATION_DELAY_MEASUREMENT,
} sai_switch_extensions_attr_t;

typedef enum _sai_tam_event_extensions_attr_t {
  SAI_TAM_EVENT_ATTR_FAKE_SWITCH_EVENT_TYPE = SAI_TAM_EVENT_ATTR_END,
  SAI_TAM_EVENT_ATTR_FAKE_DEVICE_ID,
  SAI_TAM_EVENT_ATTR_FAKE_SWITCH_EVENT_ID,
  SAI_TAM_EVENT_ATTR_FAKE_EXTENSIONS_COLLECTOR_LIST,
  SAI_TAM_EVENT_ATTR_FAKE_PACKET_DROP_TYPE_MMU,
  SAI_TAM_EVENT_ATTR_FAKE_AGING_GROUP,
  SAI_TAM_TRANSPORT_ATTR_FAKE_SRC_MAC_ADDRESS = SAI_TAM_TRANSPORT_ATTR_END,
  SAI_TAM_TRANSPORT_ATTR_FAKE_DST_MAC_ADDRESS,
} sai_tam_event_extensions_attr_t;

typedef enum _sai_port_extensions_attr_t {
  SAI_PORT_ATTR_EXT_FAKE_SYSTEM_PORT_ID = SAI_PORT_ATTR_CUSTOM_RANGE_START,
  SAI_PORT_ATTR_SERDES_LANE_LIST,
  SAI_PORT_ATTR_STATIC_MODULE_ID,
  SAI_PORT_ATTR_DIAGNOSTICS_MODE_ENABLE,
  SAI_PORT_ATTR_RX_LANE_SQUELCH_ENABLE,
  SAI_PORT_ATTR_FDR_ENABLE,
  SAI_PORT_ATTR_CRC_ERROR_TOKEN_DETECT,
  SAI_PORT_ATTR_PORT_PG_PKT_DROP_STATUS,
  SAI_PORT_ATTR_FABRIC_SYSTEM_PORT,
  SAI_PORT_ATTR_RESET_QUEUE_CREDIT_BALANCE,
  SAI_PORT_ATTR_PFC_MONITOR_DIRECTION,
} sai_port_extensions_attr_t;

typedef enum _sai_ingress_priority_group_extensions_attr_t {
  SAI_INGRESS_PRIORITY_GROUP_ATTR_LOSSLESS_ENABLE =
      SAI_INGRESS_PRIORITY_GROUP_ATTR_CUSTOM_RANGE_START,
} sai_ingress_priority_group_extensions_attr_t;

typedef enum _sai_next_hop_group_extensions_attr_t {
  SAI_NEXT_HOP_GROUP_ATTR_ARS_NEXT_HOP_GROUP_META_DATA =
      SAI_NEXT_HOP_GROUP_ATTR_CUSTOM_RANGE_START,
} sai_next_hop_group_extensions_attr_t;

typedef enum _sai_ars_profile_extensions_attr_t {
  SAI_ARS_PROFILE_ATTR_EXTENSION_ECMP_ARS_MAX_GROUPS =
      SAI_ARS_PROFILE_ATTR_CUSTOM_RANGE_START,
  SAI_ARS_PROFILE_ATTR_EXTENSION_ECMP_ARS_BASE_INDEX,
  SAI_ARS_PROFILE_ATTR_ROUTE_ARS_ALTERNATE_MEMBERS_META_DATA,
  SAI_ARS_PROFILE_ATTR_ROUTE_ARS_META_DATA_MASK,
  SAI_ARS_PROFILE_ATTR_ROUTE_ARS_PRIMARY_MEMBERS_META_DATA,
} sai_ars_profile_extensions_attr_t;

typedef enum _sai_acl_entry_extensions_attr_t {
  SAI_ACL_ENTRY_ATTR_ACTION_L3_SWITCH_CANCEL =
      SAI_ACL_ENTRY_ATTR_CUSTOM_RANGE_START,
} sai_acl_entry_extensions_attr_t;

#define SAI_ACL_ACTION_TYPE_L3_SWITCH_CANCEL \
  SAI_ACL_ENTRY_ATTR_ACTION_L3_SWITCH_CANCEL
